Main memory is in modern computing systems a key component in terms of access speed to data, availability and consistency of data, as well as security. The current trend is to install more and more main memory capacity, in order to avoid paging data in and out from/to slower mass storage devices. In-memory computing has even more increased the requirement for large amounts of main memory.
Main memory is typically implemented in form of DRAMs (dynamic random access memories). These memory devices require a regular refresh of the data. It is known that DRAM refresh is expensive in terms of both, time and energy, and its overhead is getting worse. The cost of DRAM refresh grows linearly with the capacity, which means exponentially with each density generation of memory chips. Modern JEDEC (formerly Joint Electron Device Engineering Council, today JEDEC Solid-State Technology Association) synchronous DRAM (in short SDRAM) use a special auto-refresh command that is opaque to an external memory controller and that handles all refresh operations and timing internally, i.e., internal in the DRAM chip itself.
In order to offset some of the increasing refresh overheads, JEDEC designed the auto-refresh function that uses a highly optimized architecture internally—in particular, the architecture violates the inter-operating timing rules that external controllers must fulfil and obey during normal operation (e.g., for bank PREcharge, row ACTivate and/or column read/write operations). The DRAM can violate external timing parameters internally because during refresh it is understood that, unlike “normal” operations, a read or write operation will not follow the (multi-row) ACTivate operation. The internal mechanism refreshes numeral rows simultaneously (not just one at a time like the external ACT and PRE commands). For the internal auto-refresh function there are no command/address bus constraints. A typical example of an SDRAM is the widely used DDR3 memory.
There exists a large body of research, developing schemes for manual/external refresh of DRAMs row-by-row, characterizing each row's ability to retain data and eliminating unnecessary refresh operations on rows that can be refreshed less often. These schemas have been shown to be very effective because the elimination of the refresh improves both energy and performance of the memory system. This has offered the potential of significant gains in DRAM system efficiency.
However, these schemes are incompatible with the modern auto-refresh functions of JEDEC SDRAM specifications. In addition, auto-refresh cannot skip any row, whether that row needs to be refreshed or not.
Thus, the manual/external schemes use explicit row-level Activate (ACT) and Precharge (PRE), and still refresh row-by-row, called Row Granular Refresh (RGR). And because of this, studies have shown that these refresh schemes are unable to exploit the optimizations available internally through the auto-refresh mechanism.
Previous work has promised minimal alterations to the DRAM architecture and protocol, allowing both, row granular protocol of external refresh operations and the use of the internal optimizations (K. K.-W Chang, D. Lee, Z. Chrishti, A. R. Alameldeen, C. Wilkerson, Y. Kim and O. Multu: “improving DRAM performance by parallelizing refresh with accesses” in high-performance computer architecture (HPCA), 2014 IEEE 20th International Symposium, 2014).
Other previous work has also claimed it may be impossible to equal the performance and energy savings of optimized auto-refresh by using individual ACT and PRE, commands, i.e., RGR; compare I. Bhati, Z. Chishti, S.-L. Lu and B. Jacob, “Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions,” in Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015; and I. Bhati, M.-T. Chang, Z. Chishti, S.-L. Lu and B. Jacob, “DRAM Refresh Mechanisms, Trade-offs, and Penalties,” Computers, IEEE Transactions on, vol. PP, no. 99, pp. 1-1, 2015.
Thus, there is a need for the obviously contradictory internal and external refresh mechanisms which seem to exclude each other.